Design for Test: What Your CM Needs Before It Can Test Your Board
A board arrives at assembly with its test strategy already decided. Not proposed, decided. Whatever electrical access the layout provides is the only access any test system will ever have, and no amount of process engineering on the manufacturing side adds a probe point that was never placed. Design for test is therefore a layout activity with a manufacturing consequence, and the window to get it right closes when the Gerbers are released.
The cost of getting it wrong has moved. Component pricing and lead times have tightened through 2026 across microcontrollers, memory, and passive components, which changes the arithmetic on a failed board. A unit that fails final test used to represent rework hours. When the parts on it are on extended lead time, that same unit represents a schedule slip, because the replacement components are not sitting on a shelf. Test coverage is worth more this year than it was last year, and it is bought at layout.
What Each Test Method Can Actually Reach
Four methods dominate electronics assembly, and each makes a different demand on your design.
| Method | What it needs from your layout | Where it fits |
|---|---|---|
| In-circuit test (bed of nails) | A probe pad on nearly every net, single-sided access, tooling holes | Volume production, where fixture cost amortizes |
| Flying probe | Exposed copper or pads, no fixture required | Prototypes and low volume, slower per board |
| Boundary scan | Compliant devices and a JTAG chain routed to an accessible header | Dense BGA boards where physical probing is impossible |
| Functional test | An edge connector or test header, plus defined stimulus and response | Final verification of behaviour rather than structure |
Boundary scan deserves a note on status. IEEE 1149.1, the Test Access Port and Boundary-Scan Architecture standard, was last revised in 2013.1 IEEE moved it to inactive-reserved status on March 21, 2024, which means it is no longer actively maintained.2 It remains implemented in an enormous installed base of silicon and remains the practical route to testing interconnects under a BGA. Treat the inactive designation as a maintenance status, not an obsolescence warning.
Bare board testing sits upstream of all of this and is governed separately by IPC-9252B, which defines test levels, parameters, and fixturing for unpopulated boards and inner layers.3 A board that passes bare board test can still fail as an assembly, and the two results answer different questions.
The Access Rules Your Layout Has to Respect
Fixture probes are physical objects with physical tolerances. The numbers below reflect common practice across test fixture design and are the values we work to when reviewing a package.4
- Test pad diameter: 1.0 mm (40 mil) preferred, 0.8 mm (32 mil) minimum.
- Center-to-center spacing: 1.9 mm (75 mil) preferred for standard probes, 1.27 mm (50 mil) minimum with fine-pitch probes.
- Clearance to the nearest component: 1.5 mm preferred, 1.0 mm minimum. Tall parts need more, scaling roughly with height once a component passes 10 mm.
- Board edge keep-out: 5 mm preferred, 3.175 mm minimum, because the fixture has to hold the board somewhere.
- Vias used as test points: pad diameter 1.0 mm with a finished hole no larger than 0.5 mm, so the probe tip cannot drop into the barrel.
- Tooling holes: at least two, over 2 mm diameter, in opposite corners.
One decision outweighs all six. Put every test point on one side of the board. Dual-sided access requires a clamshell fixture and roughly doubles fixture cost.4 On a design where a handful of nets are stranded on the wrong side, moving those few vias is a cheaper change than the fixture they would otherwise require.
How to Measure Coverage Honestly
Most coverage claims are a single percentage with no stated denominator, which makes them impossible to compare between two test strategies or two revisions of the same board.
The structural test community solved this with a defect-spectrum model. Devices are scored on five properties: Presence, Correctness, Orientation, Live, and Alignment. Connections are scored on three: Shorts, Opens, and Quality. Each property gets full cover, partial cover, or no cover, scored 1, 0.5, or 0, and the results are weighted and averaged rather than collapsed into one number.5 The value of the model is that it exposes what a passing test did not look at. A test can report high coverage while never verifying that a correctly soldered device is the correct device.
Functional test needs its own categories, because it verifies behaviour rather than structure. An iNEMI working group extended the framework in 2007 with categories covering feature testing, at-speed testing, parallel testing, and measurement.6
Ask your contract manufacturer which properties a proposed test plan covers, not what percentage it claims. The answer tells you where the escapes will come from.
What Your Design Package Should Include
A design package that supports test review contains six things beyond the usual fabrication and assembly data.
- A netlist, preferably in IPC-D-356A format, so test access can be verified against nets rather than inferred from copper.
- A test point report listing net name, coordinate, and board side.
- A coverage target tied to the product class and its field consequences.
- The expected test method and a volume forecast, since the fixture decision follows volume.
- BSDL files and the boundary scan chain order for every compliant device.
- Your bare board electrical test requirement, referenced to IPC-9252B.3
Sending these at quotation rather than at build turns test into a design review item, which is the only stage where it is cheap to fix.
We review test access as part of design for manufacturing on every package we quote, and we run in-circuit, flying probe, and functional test after assembly. The useful time to have that conversation is before the layout is locked, when moving a via still costs nothing and the fixture has not been built. Learn more about our Post Manufacturing Testing and Development → https://www.circuits-central.com/services-capabilities/post-manufacturing-testing-development/
"A test point you did not place is a defect you will not find."
One-page summary:
Talk to us about test access before your layout is locked. We review test point coverage as part of our design for manufacturing check, and we run in-circuit, flying probe, and functional test in house. Email info@circuits-central.com, call 1 (888) 821-7746, or send us your files for a quote.
Sources
-
"IEEE Standard for Test Access Port and Boundary-Scan Architecture", IEEE Standards Association, 2013-05-13 ↩
-
"IEEE 1149.1-2013 standard status", IEEE Standards Association, inactivated 2024-03-21 ↩
-
"IPC 9252B-2016, Requirements for Electrical Testing of Unpopulated Printed Boards", ANSI Webstore, 2016 ↩↩
-
"SMD Test Points and Design-for-Test Guidelines for PCBAs", FixturFab, accessed 2026-09-10 ↩↩
-
"PCOLA/SOQ Test Coverage in XJTAG, Part 1", XJTAG, 2019-10 ↩
-
"Functional Test Coverage Assessment, Statement of Work", iNEMI Board and Systems Manufacturing Test TIG, 2007-02-20 ↩
